The present invention relates generally to semiconductor devices and particularly to silicon on insulator (SOI) devices intended for applications in a radiation environment. The method of the present invention is described with reference to SOI structures having a buried oxide layer. Those knowledgeable in the art will recognize that the invention is not restricted to buried oxide structures but will apply to silicon on sapphire and other SOI material alternatives. Examples of alternatives include bond and etch SOI (BESOI, made by wafer bonding and etch back process) and zone melting recrystallization (ZMR) SOI materials.
High dose oxygen implantation at 200 keV into single-crystalline silicon wafers with a substrate temperature greater than 600.degree. C. followed by very-high-temperature annealing between 1,300.degree. C. and 1,350.degree. C. is now a well established technique for fabrication of SOI structures. These structures are ideal for making CMOS devices such as SRAMs for use in harsh radiation environments. For CMOS devices, the gate oxide, the isolation oxide, and the buried oxide are sensitive to radiation. Most of the investigations in the past have concentrated on the gate oxide and isolation or field oxides. The method of the present patent application is directed toward the electrical characteristics of the buried oxide.
Semiconductor fabricating companies typically obtain wafers from a separate supplier and then perform certain processes on these wafers to produce integrated circuits (IC's). SOI wafers received by a semiconductor fabricating company from their wafer supplier typically undergo certain tests as part of receiving inspection procedures. The specific test procedures are dependent on the particular application. However it is in the interest of the IC fabricator to reliably determine whether certain wafers are acceptable for their intended application with low cost receiving inspection tests where feasible.
An example will illustrate the need for efficient receiving inspection. A supplier of radiation insensitive complimentary metal oxide semiconductors (CMOS) IC's will purchase, for example, SOI wafers that include a top silicon layer, a silicon dioxide layer and a silicon substrate. In the past little has been known about the intrinsic electrical characteristics of the buried oxide front interface, i.e., the back channel. To investigate the back channel radiation characteristics in the past it has been necessary to fabricate the CMOS test structures, that is go through the semiconductor processing steps including many masks, implanting processes and high temperature annealing cycles necessary to the IC fabrication. Often the implantation process causes damage to the buried oxide and causes a degrading of its intrinsic insensitivity to radiation.
Thus a need exists for a method for determining, using relatively low cost receiving inspection tests, whether the characteristics of the silicon dioxide layer are such that it will have the required insensitivity to radiation.